--叶佳豪 201841052073
--24进制 BCD码加法计数器
--***************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************************
ENTITY COUNT_BCD24 IS
    PORT(
			CLK,CLR		:IN STD_LOGIC;
			Q 			:OUT STD_LOGIC_vector(7 downto 0);
			TCN			:OUT STD_LOGIC
		);
END COUNT_BCD24;
--**************************************************
ARCHITECTURE RUN OF COUNT_BCD24 IS
SIGNAL QQ : std_logic_vector(7 downto 0);
BEGIN
	PROCESS(CLK,CLR)
	BEGIN
		IF CLR = '0' THEN QQ <= "00000000";
		ELSIF clk'EVENT AND clk = '1' THEN
			TCN<='0';
			IF QQ >= "00100011" THEN QQ <= "00000000";TCN<='1';		--超过23就复位
			ELSIF QQ(3 downto 0) >= "1001" THEN						--十位进位
				QQ(3 downto 0) <= "0000";
				QQ(7 downto 4) <= QQ(7 downto 4) + 1;
			ELSE QQ <= QQ + 1;							--个位进位
			END IF;
			
		END IF;
		
	END PROCESS;
Q <= QQ;
END RUN;
	
